The present disclosure relates generally to image sensors and, more particularly, some embodiments of the present invention relate to pixel architectures that are well-suited for implementing subdiffraction-limit (SDL) pixels, single-bit photoelectron counting pixels that may be used in a Quanta Image Sensor (QIS), and multi-bit photoelectron counting pixels that may be used in a quantized Digital Integration Sensor (qDIS).
In a conventional CMOS active pixel sensor with intra-pixel charge transfer, the photodetecting element is typically a pinned photodiode (PPD), and the signal charge integrated in the PPD is completely transferred to a floating diffusion (FD) node by pulsing a transfer gate (TG). The FD potential must be reset (typically by a reset transistor, just prior to transfer) to a voltage (reset voltage) that is sufficiently high such that when TG is turned on, signal charge passively and completely flows from the PPD, under the TG, and into the FD. At lower FD reset voltages, the signal charge may not transfer completely because the FD becomes “filled” with signal charge before all of the signal charge is transferred. Thus, careful circuit design is required to ensure sufficiently high voltage reset of the FD, sometimes requiring the use of overvoltages or bootstrapping. Increasing the full well of the sensor exacerbates these problems, as both the depth of the PPD well is increased, and the capacity of FD must also be increased by increasing the FD capacitance and/or reset voltage.
In the case of novel image sensor concepts such as the Digital Integration Sensor (DIS), quantized Digital Integration Sensor (qDIS), or the quanta image sensor (QIS) where full well capacity is intentionally reduced, some of the complexity of pixel design is transferred to high speed readout design. While the lower full-well requirement may provide some additional flexibility in considering ways of further shrinking the pixel to achieve higher density, providing pixels for such novel image sensors nonetheless presents many unique and new challenges as well as opportunities for technical developments to provide for high quality and performance; in other words, many technical issues and problems arise that are simply not present, or not an issue, in current state-of-the art image sensors.
For example, image sensors such as QIS, qDIS, and DIS require pixels that are highly sensitive to photoelectrons. In some implementations (e.g., QIS), photoconversion of only one or several photons must generate a voltage change that is large enough to be detected, meaning that the charge-to-voltage conversion gain may need to be more than 0.5 mV/e−, possibly as much as or more than 1 mV/e−. And, generally, simply scaling a conventional CMOS image sensor pixel will not necessarily provide the sensitivity required for implementing QIS, qDIS, and DIS image sensors.